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INTEGRATED CIRCUITS
74ALS112A Dual J-K negative edge-triggered flip-flop
Product specification IC05 Data Handbook 1996 June 27
Philips Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPICAL SUPPLY CURRENT (TOTAL) 3.0mA
PIN CONFIGURATION
CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1
SF00103
TYPE 74ALS112A
TYPICAL fMAX 50MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 74ALS112AN 74ALS112AD DRAWING NUMBER
16-pin plastic DIP 16-pin plastic SO
SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS CP0, CP1 J0, J1 K0, K1 SD0, SD1 RD0, RD1 Q0, Q1, Q0, Q1 DESCRIPTION Clock Pulse input (active falling edge) J inputs K inputs Set inputs (active-Low) Reset inputs (active-Low) Data outputs 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/2.0 1.0/2.0 1.0/2.0 1.0/2.0 20/80 LOAD VALUE HIGH/LOW 20A/0.1mA 20A/0.2mA 20A/0.2mA 20A/0.2mA 20A/0.2mA 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20A in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
3 11 2 12
IEC/IEEE SYMBOL
3 1 1 4 15 13 10 14 J0 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1 11 13 12 14 10 VCC = Pin 16 GND = Pin 8 5 6 9 7 J1 K0 K1 2 15 4
1J C1 1K R S
5
6
2J C2 2K R S 7 9
SF00104
SF00105
1996 Jun 27
2
853-1846 16995
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
LOGIC DIAGRAM
5, 9 Qn
6, 7 Qn
4, 10 SDn 2, 12 Kn
15, 14 RDn 3, 11 Jn
VCC = Pin 16 GND = Pin 8
1, 13 CPn
SF00106
FUNCTION TABLE
INPUTS SD L H L H H H H H RD H L L H H H H H CP X X X H J X X X h h l l X K X X X h l h l X OUTPUTS OPERATING MODE Q H L H* q H L q q Q L H H* q L H q q Asynchronous Set Asynchronous Reset Undetermined * Toggle Load "1" (Set) Load "0" (Reset) Hold "no change" Hold "no change"
H = High voltage level h = High state must be present one setup time prior to High-to-Low clock transition L = Low voltage level l = Low state must be present one setup time prior to High-to-Low clock transition q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition X = Don't care = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock. Simultaneous Low on both SD and RD makes both Q and Q High.
1996 Jun 27
3
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 16 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -0.4 8 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH VO OL VIK II IIH IIL IO ICC PARAMETER High-level output voltage TEST CONDITIONS1 MIN VCC = 10%, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN Input clamp voltage Input current at maximum input voltage High-level input current CPn Low-level input current Output current3 Supply current (total) SDn, RDn, Jn, Kn VCC = MAX, VI = 0.4V VCC = MAX, VO = 2.25V VCC = MAX -30 2.5 VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V IOH = -0.4mA IOL = 4mA IOL = 8mA VCC - 2 0.25 0.35 -0.73 0.40 0.50 -1.5 0.1 20 -0.1 -0.2 -112 4.5 LIMITS TYP2 UNIT MAX V V V V mA A mA mA mA mA
Low-level Low level output voltage
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
1996 Jun 27
4
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn or RD to Qn or Qn Waveform 1 Waveform 1 Waveform 2, 3 35 2.0 4.0 1.5 3.5 10.0 10.5 8.0 9.5 MAX MHz ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (L) tREC Setup time, High or Low Jn, Kn to CPn Hold time, High or Low Jn, Kn to CPn CPn Pulse width high or Low SDn or RDn Pulse width Low Recovery time, SDn or RDn to CPn Waveform 1 Waveform 1 Waveform 1 Waveform 2, 3 Waveform 2, 3 8.0 8.0 0.0 0.0 11.0 8.0 6.0 8.0 MAX ns ns ns ns ns UNIT
1996 Jun 27
5
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
AC WAVEFORMS
For all waveforms, VM = 1.3V. The sahded areas indicate when the input is permitted to change for predictable output performance.
Jn, Kn
VM tsu(L)
VM th(L) 1/fmax
VM tsu(H)
VM th(H)
CPn
VM
tw(L)
VM tw(H)
VM tPHL
tPLH Qn VM tPHL Qn VM
VM tPLH VM
SC00136
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Pulse Width, and Maximum Clock Frequency
Jn, Kn
Jn, Kn
SDn
VM
tw(L) VM tREC
RDn
VM
tw(L) VM tREC
CPn
VM
CPn tPHL
VM
tPLH Qn tPHL Qn VM Qn VM Qn tPLH VM VM
SC00049
SC00050
Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock
1996 Jun 27
6
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tff) CL RL tw VM 10% tTLH (tr ) 0.3V 90% AMP (V)
tTLH (tr ) 90%
tTHL (tf ) AMP (V) 90% VM tw 10% 0.3V
Test Circuit for Totem-pole Outputs
POSITIVE PULSE 10%
VM
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate 1MHz tw 500ns tTLH 2.0ns tTHL 2.0ns
SC00005
1996 Jun 27
7
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1996 Jun 27
8
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Jun 27
9
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1996 Jun 27 10

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